Integrated thermal characterization and trim of polysilicon resistive elements

ABSTRACT

Devices, systems, and methods for providing an on-chip, temperature-stable resistance network for generating a precision current or precision resistance are disclosed. The resistance network includes a first resistance material having a linear, negative temperature coefficient of resistance and a second resistance material having a linear, positive temperature resistance. The first and second resistance materials are arrayed in segments proximate to a local, pulsed thermal gradient and are combined or mixed, i.e., trimmed, to provide a zero or near zero thermal coefficient.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. provisional patent application No. 60/722,279 filed on Sep. 30, 2005, which is incorporated herein in its entirety by reference.

STATEMENT REGARDING FERERALLY SPONSORED RESEACH OR DEVELOPMENT

(Not Applicable)

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to trimming polysilicon resistive elements and, more particularly, to trimming polysilicon resistive elements by adjusting the “resistive mixture” of plural polysilicon segments having uniform or linear thermal coefficients of resistance of opposite signs.

2. Summary of the Related Art

Integrated circuits (IC), especially analog integrated circuits, need precise, temperature-stable voltage and/or current sources that are processed independently. Traditionally, very precise voltage sources can be produced, e.g., using bandpass or buried Zener circuitry. However, precise current sources that exhibit both process stability and temperature stability are more difficult to manufacture on-chip partially due to the lack of precision resistive components in most IC processing.

Available resistive components used in conventional IC processing have very large temperature coefficients, e.g., measured in the 1000's of ppm/° C., and large process tolerances, e.g., ± 30 percent. Accordingly, heretofore, ICs requiring a precision current source have had to rely on external, i.e., off-chip, reference resistance in combination with on-chip voltage reference.

Existing methods of providing precise, on-chip current sources rely on either using a very accurate, resistive material, e.g., thin films of chromium-based metals, and/or combining lower-accuracy solid-state devices in such a way as to provide a final device with a high-degree of accuracy, which is to say, with a low temperature coefficient (TC) and a tight tolerance.

Establishing a process with a very accurate, resistive material, however, requires additional, expensive processing, typically involving additional process masks and fabrication steps. Combining lower-accuracy devices to produce a higher-accuracy device requires testing due to the electrical characteristics of the opposing TC poly-materials, which do not necessarily track each other due to manufacturing tolerances, and, further, requires trimming of the silicon wafer or the resulting, packaged device at multiple temperatures.

Combining or mixing positive TC current sources and negative TC current sources to provide a zero or near-zero TC current source is known in the art. However, verification of the proper “resistance mixture” to achieve the desired zero or near-zero TC mix without having to trim any “over temperature” remains problematic.

Therefore, it would be desirable to provide devices and systems that use readily-available, lower-accuracy solid-state components and standard IC processes to provide a repeatable, precision, zero or near-zero TC, poly-silicon resistance network that provides an optimal “resistance mixture” of opposing TC poly-materials without requiring undue “over temperature” trimming. More particularly, it would be desirable to combine or to mix opposing TC poly-materials having uniform/linear temperature coefficients of resistance and identical thermal mass and thermal conductivity properties.

It would be further desirable to include the devices on-chip as current sources for any IC requiring a precision resistance or a precision current. More specifically, it would be desirable to provide a precision current source to enable power over the Ethernet applications.

BRIEF SUMMARY OF THE INVENTION

An on-chip, temperature-stable resistance network for generating a precision current or a precision resistance is disclosed. The resistance network includes a first resistance material, e.g., a high-sheet rho poly-silicon resistance material, arrayed in a first plurality of segments on the chip and a second resistance material, e.g., a medium-sheet rho poly-silicon resistance material, arrayed in a second plurality of segments on the chip. The temperature coefficient of resistance of the second resistance material and the temperature coefficient of resistance (TCR) of the first resistance material have opposite signs so that, when combined in the network, the opposing TCRs produce a net resistance variation of zero as the network's overall temperature changes. In addition, this resistance network is constructed in such a way as to respond to only the average value of either external or local, linear thermal gradients.

In one aspect of the resistance network, a resistive heater element, e.g., a metal heater coil, provides a local thermal gradient to the resistance network. The resistive heater element is disposed directly above or directly below the resistance network to promote thermal coupling. Thermal coupling-provides a fast thermal response time, e.g., less than about 100 microseconds, between about 20 microseconds and about 50 microseconds, to resistance network value changes. The resistive heater element is energized and the pulse amplitude is controlled, to provide a uniform and symmetrical thermal gradient, e.g., a local temperature between about 30 degrees Centigrade and about 60 degrees Centigrade above the average temperature of the chip. optionally, a shield, e.g., a metal, grounded or electrically-driven Faraday shield, can be interposed between the resistive heater element and the network to reduce capacitive coupling and to increase thermal uniformity across the resistance network surface. This shield can be grounded or electrically-driven to a static or dynamic potential.

A circuit for providing a precision current source is also disclosed. The circuit includes a temperature-stable resistance network; a resistive heater element for providing a local thermal gradient; a trim controller for changing the temperature coefficient of resistance of the resistance network; and an absolute (or overall) trim controller for changing the temperature coefficient of resistance of the resistance network without altering the precision current circuit's overall temperature coefficient.

In one aspect of the precision current source, the circuit includes a mixture trim controller, e.g., a four-bit trim controller such as a current mirror and a current splitter. The mixture trim controller changes or adjusts the absolute (or overall) TCR of the resistance network to zero or near-zero. More specifically, the mixture trim controller varies or adjusts the number of first resistance material segments and the number of second resistance material segments in the “resistive mixture” of the resistance network so that the TCR of the resistance network is zero or near-zero. The mixture trim controller controls the TCR of the resistance network and the resulting overall TCR of the precision current circuit's current.

In yet another aspect of the precision current source, the precision current source also includes an absolute (or overall) trim controller for changing the output current. The absolute (or overall) trim controller trims the output current without altering the overall TCR.

A method of providing a precision current source or of providing a precision resistance on-chip to an integrated circuit is also disclosed. The method includes providing an on-chip resistance network that includes a first resistance material arrayed in a first plurality of segments and a second resistance material arrayed in a second plurality of segments; determining initial current and resistance properties of each resistance material of the first and second plurality of segments;

applying a local thermal gradient to the resistance network; adjusting an overall TCR of the resistance network by adjusting the number of first resistance material segments and the number of second resistance material segments in a “resistance mixture”; and adjusting the output current by trimming the applied voltage to the resistance network.

Adjusting the overall TCR of the resistance network includes determining post-energizing current and resistance properties of each resistance material of the first and second plurality of segments; comparing initial current values with post-energizing current values; and adjusting the number of first and second resistance material segments in the “resistance mixture”.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.

FIG. 1 shows a circuit for providing a precision current source or for providing a precision resistance in accordance with the present invention;

FIG. 2 shows a resistance network of a plurality of poly-resistors with opposing temperature coefficients in accordance with the present invention; and

FIG. 3 shows a flow diagram of a method of providing a zero or near-zero temperature coefficient precision current source in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention describes devices, systems, and methods for providing an on-chip, zero or near-zero temperature coefficient of resistance (TCR) resistor or a zero or near-zero temperature coefficient current source, or current reference. The disclosed devices, systems, and methods combine or mix an array of resistive materials having positive temperature coefficients of resistive with an array of resistance materials having negative, i.e., opposing, temperature coefficients of resistance (TCR) so that, when combined in a resistance network, e.g., in a “resistance mixture”, the TCR with opposing signs, i.e., the “opposing TCRs”, cancel one another. More specifically, the present invention describes an on-chip, temperature-stable, resistance network for generating a precision current or a precision reference circuit.

Referring to FIG. 1, there is shown circuitry for a high-precision, on-chip, bias current source 10 in accordance with the present invention. The current source 10 comprises an on-chip, temperature-stable, resistance network 20, a heating element 25, a “resistance mixture” trim controller 12, and an absolute (or overall) resistance trim controller 14.

As shown in FIG. 2, the temperature-stable, resistance network 20 includes a first resistance material 22 that is arrayed in a first plurality of segments and a second resistance material 24 that is arrayed in a second plurality of segments. The arrangement shown in FIG. 2 corresponds to a common centroid configuration, however, this arrangement is shown illustratively and is not to be construed as limiting the invention thereto.

The first and second resistance materials 22 and 24 can be poly-silicon resistors and the like. Although poly-silicon resistors generally have poor TCRS and poor absolute thickness tolerances, doping levels of the poly-silicon resistors can be structured and arranged to produce suitable MSR and HSR poly-silicon resistors 24 and 22. Advantageously, poly-silicon resistors have extremely uniform or linear TCRs. Furthermore, poly-silicon resistors have minimal extraneous parasitics residing in the dielectric layers that are disposed above the bulk silicon.

In one aspect of the present invention, one of the resistance materials in the resistance network 20, e.g., the first resistance material 22, is a high-sheet rho (HSR) poly-silicon resistor and the other resistance material in the resistance network 20, e.g., the second resistance material 24, is a medium-sheet rho (MSR) poly-silicon resistor. MSR poly-silicon resistors 24 and HSR poly-silicon resistors 22 have identical or substantially identical thermal properties, such as thermal mass, thermal resistance, and thermal conductivity, but have positive TCRs and negative TCRs, respectively.

For example, when a MSR poly-silicon resistor 24 is heated, resistance increases uniformly or linearly at about +800 ppm/° C. In contrast, when a HSR poly-silicon resistor 22 is heated, resistance decreases uniformly or linearly at about −400 ppm/° C.

Advantageously, according to one aspect of the present invention, the combination or mixture of positive TCR, MSR poly-silicon resistors 24 and negative TCR, HSR poly-silicon resistors 22 in the resistance network 20 can be adjusted continuously to provide a zero or near-zero overall network temperature coefficient of resistance. Moreover, the first resistance material 22 and the second resistance material 24 can also be structured and arranged to negate external thermal gradient effects when exposed to a local thermal gradient.

In another aspect of the present invention, the local thermal gradient is provided by a resistive heater element 25 or thermal gradient generator, e.g., an array of one or more heater coils. The resistive heater element 25 can be manufactured of a lightweight, electrically-conductive metal, e.g., aluminum and aluminum alloys.

The resistive heater element 25 is disposed directly above the MSR poly-silicon resistors 24 and HSR poly-silicon resistors 22 in the resistance network 20 (or, alternatively, directly below the resistance network 20, if the substrate or die is inverted). Disposing the resistive heater element 25 directly above (or directly below) the resistance network 20 promotes better thermal coupling while, importantly, confining the heating element 25 to a small percentage of the overall circuit area so that just the resistance network 20 is heated.

Very tight thermal coupling ensures a uniform and symmetrical thermal gradient on both the negative TCR portion 22 and the positive TCR portion 24 of the resistance network 20. Thermal coupling also allows fast, first-order thermal response time constants in the range between about 20 and about 50 microseconds (μsec). As a result, the settling time is less than about 100 μsec, which does not significantly impact testing and trimming time.

Desirably, once the resistive heater element 25 is energized, the local temperature of the resistance network 20 is between about 30° C. and about 60° C. above the average temperature of the bulk silicon substrate or die. More desirably, the average temperature of the bulk silicon substrate or die remains relatively unchanged throughout the energizing phase while the resistance network 20 is heated.

In yet another aspect of the invention, the resistive heater element 25 is energized quickly, e.g., using a voltage jump from 0 V to about 48 V, producing a thermal pulse. Energizing the resistive heater element 25 provides an abrupt change in temperature (ΔT) of the resistance materials 22 and 24 in the resistance network 20 of about 40° C. According to the present invention, temperature is set by the pulse amplitude. Thus, the ΔT is more critical that the absolute temperature (T_(max)) because the intent is to provide a repeatable temperature “look ahead” signal from which the mixture trim controller 12 can adjust the “resistance mixture” of first and second resistance materials segments 22 and 24 to achieve a zero or near-zero TCR.

The mixture trim controller 12, e.g., a four-bit controller such as a current splitter, a current mirror, and the like, adjusts and controls the “resistance mixture” of the resistance network 20 to provide the lowest, i.e., a zero or near-zero, TCR. More specifically, the mixture trim controller 12 extrapolates the optimal combination or mixture of first resistance material segments 22 and second resistance material segments 24 that, in a discrete combination or “resistance mixture”, provide a zero or near-zero TCR.

For example, the mixture trim controller 12 uses known TCR data for each of the various resistance materials segments 22 and 24 and, further, samples the change in temperature (ΔT) after the resistive heater 25 is energized. By energizing the resistive heater element 25 quickly and heating the resistance network 20 abruptly, the overall TCR of the resistance network 20 and the TCRs of resistance material segments 22 and 24 can be measured quickly at various temperatures. Using these data, the mixture trim controller 12 can extrapolate or forecast an optimal resistance network 20 arrangement consistent therewith. The mixture trim controller 12 changes the overall TCR of the resistance network 20 by adding or deleting the number of the first resistance material segments 22 and the number of second resistance material segments 24 comprising the resistance network 20.

More specifically, the mixture trim controller 12 proportionally “trims” the number of segments or groups of the negative temperature coefficient elements 22 and the number of segments or groups of positive temperature coefficient elements 24 in the “resistance mixture” by measuring the output current from the resistance network 20 before and after energizing the resistive heater element 25. Advantageously, the mixture trim controller 12 changes the overall TCR of the resistance network 20 albeit without altering the circuit's 10 absolute (or overall) resistance value. To that end, the mixture trim controller 12 can include or be in operational association with a standard fuse, a poly-fuse bus, an EE bus, and the like.

Optionally, a heat spreader (not shown), e.g., a grounded, metal or an electrically-driven Faraday shield, can be interposed between the resistive heater element 25 and the resistance network 20. The heat spreader reduces capacitive coupling therebetween and increases thermal uniformity across the network 20 surface. The Faraday shield electrically shields the resistance network 20 from the switching noise that resides on the heater element 25 while the heater coil of the resistive heater element 25 is being energized.

The disclosed precision current source 10 also includes an absolute (or overall) trim controller 14. The absolute (or overall) trim controller 14 is provided to change, e.g., by trimming, the resultant value of the TCR of the resistance network 20 once the TCR of the “resistance mixture” has stabilized. The absolute (or overall) trim controller 14 is structured and arranged to trim the value of the resultant output circuit parameter without altering the resistance network's 20 overall TCR. More specifically, the absolute (or overall) trim controller 14 proportionally adjusts the current components, i.e., the output current, of the first resistive materials 22 and second resistive materials 24 in the “resistance mixture”.

Having described a resistance network 20 and precision current circuitry 10 using the resistance network 20 to provide a precision, on-chip current source, or current reference, a method of providing on-chip, precision current will be described. Referring to FIG. 3, there is shown a flow diagram for providing the same.

In a first step, a resistance network is provided on the chip (STEP 1). In one aspect of the invention, the resistance network includes a first resistance material arrayed in a first plurality of segments, and a second resistance material arrayed in a second plurality of segments such as described above. The first and second resistance materials have the same or substantially the same thermal mass and thermal resistance properties. However, the second resistance material has a temperature coefficient of resistance (TCR) opposite in sign as that of the first resistance material. To maintain uniform thermal resistance, the end contacts of each of the first and the second plurality of segments are interconnected.

In a second step, an identical voltage can be applied across each of the segments of the first and the second resistance material (STEP 2 a) and output currents can be measured or sampled for each segment or any of a plurality of groups of segments (STEP 2 b) and summed, to provide an estimate of the resistance provided by each segment or any of the groups of segments of the first and the second resistance material (STEP 2).

In a next step, a thermal gradient generator, e.g., a resistive heater, that is thermally coupled to and proximate to the resistance network is energized to apply heat to the resistance network rapidly (STEP 3). The thermal gradient generator is structured and arranged to provide a local, linear or uniform thermal gradient to the first and the second resistance materials in the resistance network (STEP 3) without significantly changing the overall temperature of the substrate or die.

In one aspect of the present method, the thermal gradient generator is thermally coupled so that when the thermal gradient generator is energized with a 48 V bias, the temperature of each of the plurality of first and second resistance member segments increases by about 50° C. to about 100° C. and the thermal time constant is less than about 100 μsec.

In a next step, the post-energizing output current can be measured or sampled (STEP 4). If there is no change in current between the pre- and post-energizing measurements, then the TCR is already zero or has been trimmed to zero and the operation is complete and the “done” position is achieved. However, if a variation or change in current is measured, sampled or detected, the “resistance mixture” of first and second resistance material segments in the resistance network is adjusted (STEP 5).

Variations in pre- and post-energizing current measurements can be adjusted using a mixture trim controller (STEP 5), e.g., a 4-bit controller such as for a current splitter, a current mirror, and the like, to change to overall TCR of the resistance network. Changing the overall TCR of the resistance network is effected by changing the number of the first resistance material segments and the number of second resistance material segments actively participating in the resistance network.

In another aspect of the present method, adjustments are “look-ahead” adjustments that use real time temperature (ΔT) and current variations to forecast or predict the optimal combination or “resistance mixture” of first and second resistance member segments that provide the lowest, i.e., zero or near zero, TCR.

Adjustment to the “resistance mixture” (STEP 5) continues until the TCR of the resistance network stabilizes. Once the TCR of the resistance network stabilizes, then the absolute (or overall) resistance value is adjusted (STEP 6). Absolute resistance trimming (STEP 6) proportionally adjusts the first and the second resistance member segments. Hence, the thickness variables can be changed without changing the temperature. As a result, the overall TCR remains unchanged. Moreover, temperature stability is limited by absolute resistance trimming and overall stability is less than about 1 percent.

While the invention is described through the above-described exemplary embodiments, it will be understood by those of ordinary skill in the art that modifications to, and variations of, the illustrated embodiments may be made without departing from the inventive concepts disclosed herein. Accordingly, the invention should not be viewed as limited, except by the scope and spirit of the appended claims. 

1. An on-chip, temperature-stable resistance network for generating a precision current or a precision resistance, the network comprising: a first resistance material arrayed in a first plurality of segments on the chip; and a second resistance material arrayed in a second plurality of segments on the chip, the second resistance material having a temperature coefficient of resistance opposite that of the first resistance material.
 2. The network as recited in claim 1, wherein the first resistance material and the second resistance material are poly-silicon resistance materials.
 3. The network as recited in claim 2, wherein the first resistance material is a first sheet rho material and the second resistance material is a second sheet rho material.
 4. The network as recited in claim 3, wherein the first resistance material is a high sheet rho material and the second resistance material is a medium sheet rho material.
 5. The network as recited in claim 1, wherein the first resistance material and the second resistance material have identical thermal mass and conduction properties.
 6. The network as recited in claim 1, wherein the first resistance material and the second resistance material are structured and arranged to negate the effects of linear, external or local thermal gradients and only respond to an average temperature of said linear, external or local thermal gradients.
 7. The network as recited in claim 6, wherein the local thermal gradient is provided by a resistive heater element that is disposed directly above or directly below the resistance network.
 8. The network as recited in claim 7, wherein the resistive heater element is structured and arranged to provide a uniform and symmetrical thermal gradient.
 9. The network as recited in claim 8, wherein a local temperature of the resistance network is about 30 degrees Centigrade to about 60 degrees Centigrade above an average temperature of the chip.
 10. The network as recited in claim 1, the network comprising further a mixture trim controller for changing an overall temperature coefficient of resistance of the network, the mixture trim controller being structured and arranged to change the number of the first plurality of segments and the number of second plurality of segments in a “resistive mixture” of the resistance network.
 11. The network as recited in claim 10, wherein the mixture trim controller is selected from the group comprising a current mirror and a current splitter.
 12. The network as recited in claim 10, wherein the mixture trim controller is structured and arranged to provide a “resistance mixture” comprising one or more of the first plurality of segments and one or more of the second plurality of segments such that the “resistance mixture” provides zero or near-zero temperature coefficient of resistance.
 13. The network as recited in claim 1, the network further comprising an absolute or overall trim controller for changing the value of a target parameter, the absolute or overall trim controller being structured and arranged to trim the value of the target parameter without altering the target parameter's overall temperature coefficient.
 14. The network as recited in claim 1, wherein the network is electrically isolated.
 15. The network as recited in claim 1, wherein the first and the second resistance materials each have a uniform thermal temperature coefficient.
 16. A circuit for providing a precision current source, the circuit comprising: a temperature-stable resistance network including: a first resistance material arrayed in a first plurality of segments, and a second resistance material arrayed in a second plurality of segments, the second resistance material having a temperature coefficient opposite that of the first resistance material; a resistive heater element that is disposed directly above or directly below the resistance network, for providing a local thermal gradient; a trim controller for changing an overall temperature coefficient of resistance of the resistance network, the trim controller being structured and arranged to change the number of the first plurality of segments in the resistance network and the number of second plurality of segments in the resistance network; and an absolute (or overall) trim controller for changing an output current of the resistance network, the absolute (or overall) trim controller being structured and arranged to trim the output current without altering the temperature coefficient of resistance of the resistance network.
 17. The circuit as recited in claim 16, wherein the first resistance material and the second resistance material are poly-silicon resistance materials.
 18. The circuit as recited in claim 16, wherein the first resistance material is a high sheet rho material and the second resistance material is a medium sheet rho material.
 19. The circuit as recited in claim 16, wherein the first resistance material and the second resistance material are structured and arranged to negate the effects of linear, external or local thermal gradients and only respond to an average temperature of said linear, external or local thermal gradients.
 20. The circuit as recited in claim 16, wherein the resistive heater element comprises one or more metal heater coils.
 21. The circuit as recited in claim 16, the circuit further comprising a shield interposed between the resistive heater element and the resistance network to reduce capacitive coupling therebetween and to increase thermal uniformity across the resistance network surface.
 22. The circuit as recited in claim 21, wherein the shield is a metal, grounded or electrically-driven Faraday shield.
 23. The circuit as recited in claim 16, wherein the resistive heater element is structured and arranged to provide a uniform and symmetrical thermal gradient.
 24. The circuit as recited in claim 23, wherein a local temperature of the resistance network is about 30 degrees Centigrade to about 60 degrees Centigrade above an average temperature of the bulk silicon.
 25. The circuit as recited in claim 16, wherein the resistive heater element is disposed proximate the resistance network to provide thermal coupling to promote a fast thermal response.
 26. The circuit as recited in claim 25, wherein the fast thermal response is between about 20 microseconds and about 50 microseconds.
 27. The circuit as recited in claim 16, wherein the trim controller is a four-bit trim controller.
 28. The circuit as recited in claim 27, wherein the four-bit trim controller is set by a standard fuse or an EE memory trim device.
 29. The circuit as recited in claim 16, wherein the trim controller changes the temperature coefficient of resistance of the resistance network.
 30. The circuit as recited in claim 16, wherein the trim controller is structured and arranged to provide a combination of the first plurality of segments and of the second plurality of segments that results in a minimal temperature coefficient of resistance.
 31. A method of providing a precision current source or a precision resistance on-chip to an integrated circuit, the method comprising: providing an on-chip resistance network that includes a first resistance material arrayed in a first plurality of segments, and a second resistance material arrayed in a second plurality of segments, the second resistance material having a temperature coefficient of resistance opposite that of the first resistance material; determining initial current and thermal coefficient of resistance properties of each resistance material of the first and second plurality of segments; applying a local thermal gradient to the resistance network; adjusting an overall temperature coefficient of resistance of the resistance network by adjusting the combination of first resistance material segments and second resistance material segments in a resistance mixture; and adjusting an absolute value of the precision current source by trimming the absolute value of the applied voltage or current excitation to the resistance network.
 32. The method as recited in claim 31, wherein providing an on-chip resistance network includes providing an on-chip resistance network that includes first and second resistance materials that have identical or substantially identical thermal mass and thermal resistance properties.
 33. The method as recited in claim 31, wherein providing the local thermal gradient includes providing very tight thermal coupling to maintain a uniform or linear thermal profile.
 34. The method as recited in claim 33, wherein providing the local thermal gradient includes providing very tight thermal coupling that enables a thermal response time to be less than about 100 microseconds.
 35. The method as recited in claim 33, wherein applying the local thermal gradient includes providing very tight thermal coupling so that when the local thermal gradient is applied, the first and second resistance members experience a change in temperature between about 50 degrees Centigrade and about 100 degrees Centigrade.
 36. The method as recited in claim 31, wherein adjusting the overall temperature coefficient of resistance of the resistance network includes: determining post-energizing current and thermal coefficient of resistance properties of each resistance material of the first and second plurality of segments; comparing initial current values with post-energizing current values; and adjusting the number of first and second resistance material segments in the resistance mixture based on results from comparing initial current values with post-energizing current values.
 37. The method as recited in claim 31, wherein adjusting the absolute value of the precision current source is performed without altering the resistance network's overall temperature coefficient of resistance.
 38. The method as recited in claim 31, wherein adjusting the absolute value of the precision current source is performed by proportionally adjusting current components of the first and second resistance material segments. 